From 45cce24f355f2b8b60d9afcd2a409c5dbb3c0fd1 Mon Sep 17 00:00:00 2001
From: Michael Dryden <mdryden@chem.utoronto.ca>
Date: Wed, 4 Feb 2015 19:01:24 -0500
Subject: [PATCH] Implemented single timed ADC measurements for DPV. Completes
#12
---
DSTAT-temp/src/experiment.c | 86 ++++++++++++++----------------------
DSTAT1.atsuo | Bin 56832 -> 56832 bytes
2 files changed, 34 insertions(+), 52 deletions(-)
diff --git a/DSTAT-temp/src/experiment.c b/DSTAT-temp/src/experiment.c
index fd4db70..8734444 100644
--- a/DSTAT-temp/src/experiment.c
+++ b/DSTAT-temp/src/experiment.c
@@ -968,59 +968,28 @@ void dpv_experiment(int16_t start, int16_t stop, uint16_t step, uint16_t pulse_h
direction = 0;
tc_enable(&TCF0);
+ tc_enable(&TCC0);
//calculate time to ADC trigger
cpu_period = ceil((double)pulse_period*1e-3*F_CPU);
- uint16_t temp_div = ceil((double)cpu_period/65536);
-
- if (temp_div == 1)
- tc_write_clock_source(&TCF0,TC_CLKSEL_DIV1_gc);
- else if (temp_div == 2)
- tc_write_clock_source(&TCF0,TC_CLKSEL_DIV2_gc);
- else if (temp_div <= 4){
- tc_write_clock_source(&TCF0,TC_CLKSEL_DIV4_gc);
- temp_div = 4;
- }
- else if (temp_div <= 8){
- tc_write_clock_source(&TCF0,TC_CLKSEL_DIV8_gc);
- temp_div = 8;
- }
- else if (temp_div <= 64){
- tc_write_clock_source(&TCF0,TC_CLKSEL_DIV64_gc);
- temp_div = 64;
- }
- else if (temp_div <= 256){
- tc_write_clock_source(&TCF0,TC_CLKSEL_DIV256_gc);
- temp_div = 256;
- }
- else if (temp_div <= 1024){
- tc_write_clock_source(&TCF0,TC_CLKSEL_DIV1024_gc);
- temp_div = 1024;
- }
- else{
- printf("#Frequency/ADC rate is too low\n\r");
- return;
- }
+ uint32_t adc_period = ceil((((double)pulse_period*1e-3)-(double)(sample_delay_ms_100div/1e5))*F_CPU);
+ uint16_t divider = set_timer_period(cpu_period, &TCF0);
+ uint16_t adc_divider = set_timer_period(adc_period, &TCC0);
- tc_write_period(&TCF0, (uint16_t)(cpu_period/temp_div));
cpu_width = (double)pulse_width*1e-3*F_CPU;
- tc_write_cc(&TCF0, TC_CCA, (uint16_t)(cpu_width/temp_div));
+ uint32_t adc_width = ceil((((double)pulse_width*1e-3)-(double)(sample_delay_ms_100div/1e5))*F_CPU);
+ tc_write_cc(&TCF0, TC_CCA, (uint16_t)(cpu_width/divider));
tc_enable_cc_channels(&TCF0, TC_CCAEN);
-
- if (direction == 1)
- max5443_set_voltage1(dacindex+dacindex_pulse_height);
- else
- max5443_set_voltage1(dacindex-dacindex_pulse_height);
+ tc_write_cc(&TCC0, TC_CCA, (uint16_t)(adc_width/adc_divider));
+ tc_enable_cc_channels(&TCC0, TC_CCAEN);
ads1255_wakeup();
- ads1255_rdatac();
- ads1255_sync();
+ ads1255_standby();
+
volt_exp_start();
TCF0.CNT = 0;
- while (!tc_is_overflow(&TCF0));
- ads1255_wakeup(); //synchronize ADC
- TCF0.CNT = 0;
+ TCC0.CNT = 0;
if (_dpv_singledir(dacindex_start, dacindex_stop, dacindex_pulse_height, dacindex_step, direction))
goto aborting; //function will return non-zero if abort called over USB
@@ -1031,7 +1000,10 @@ void dpv_experiment(int16_t start, int16_t stop, uint16_t step, uint16_t pulse_h
volt_exp_stop();
tc_write_clock_source(&TCF0, TC_CLKSEL_OFF_gc);
tc_disable(&TCF0);
+ tc_write_clock_source(&TCC0, TC_CLKSEL_OFF_gc);
+ tc_disable(&TCC0);
TCF0.CNT = 0;
+ TCC0.CNT = 0;
ads1255_standby();
return;
@@ -1059,31 +1031,41 @@ uint8_t _dpv_singledir (uint16_t dacindex, uint16_t dacindex_stop, uint16_t daci
while ((dacindex <= dacindex_stop && direction == 1) || (dacindex >= dacindex_stop && direction == 0)){
tc_clear_overflow(&TCF0);
tc_clear_cc_interrupt(&TCF0, TC_CCA);
+ tc_clear_overflow(&TCC0);
+ tc_clear_cc_interrupt(&TCC0, TC_CCA);
- while (!tc_is_cc_interrupt(&TCF0, TC_CCA)){ //convert continuously until tc CCA match - datum is last collected point
- while (ioport_pin_is_low(IOPORT_CREATE_PIN(PORTD, 5))); //wait for next valid datum
- while (ioport_pin_is_high(IOPORT_CREATE_PIN(PORTD, 5)));
- forward = ads1255_read_fast24();
+ while (!tc_is_cc_interrupt(&TCC0, TC_CCA)){ //wait until ADC TC CCA match
if (udi_cdc_is_rx_ready()){ //check for abort signal over USB
if (getchar() == 'a')
return 1;
}
}
+ ads1255_wakeup();
+ while (ioport_pin_is_high(IOPORT_CREATE_PIN(PORTD, 5)));
+ forward = ads1255_read_single24();
+ ads1255_standby();
+
+ while (!tc_is_cc_interrupt(&TCF0, TC_CCA)); //wait for end of half-cycle
+
//switch voltage to baseline
max5443_set_voltage1(dacindex);
- while (!tc_is_overflow(&TCF0)){ //wait for tc overflow
- while (ioport_pin_is_low(IOPORT_CREATE_PIN(PORTD, 5))); //wait for next valid datum
- while (ioport_pin_is_high(IOPORT_CREATE_PIN(PORTD, 5)));
- reverse = ads1255_read_fast24();
-
+ while (!tc_is_overflow(&TCC0)){ //wait for ADC TC overflow
if (udi_cdc_is_rx_ready()){
if (getchar() == 'a')
return 1;
}
}
-
+
+ ads1255_wakeup();
+ while (ioport_pin_is_high(IOPORT_CREATE_PIN(PORTD, 5)));
+ reverse = ads1255_read_single24();
+ ads1255_standby();
+
+ while (!tc_is_overflow(&TCF0)); //wait for end of half-cycle
+ TCC0.CNT = 0; // Resync ADC TC
+
lastindex = dacindex;
//increment dacindex
diff --git a/DSTAT1.atsuo b/DSTAT1.atsuo
index 27e605a947380e8b305f257e7b61f155ff94837d..c409dd7e0b88439dfd9d1cdd2b17f4b8fcedb73f 100644
GIT binary patch
delta 218
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z&r&+UCS_6Om8w~!X9bl04+X7k3=Hgy3=A9C85mN4bRZ`KgAX$U!xkQ(SwK2TfPq1m
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v&I}CefM);o0?Gnu^FRiMg+N_@f%FO_`zQZ*Qr)~FG$5YInQ`;4Eo_<qV3|Y4
delta 114
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zj}2o0YyfWnV*qOaTmX2J-3cQJb?=ey*=%*VxRa4m69F-kT}K}TL;!LCvQIz;lU`pk
UlkP$`v#3>2Ujp0!v--3KDY1(&H2?qr
--
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