diff --git a/DSTAT-temp/src/config/conf_clock.h b/DSTAT-temp/src/config/conf_clock.h
index 0f2eb959772f41744f53874643fd834ba4bec592..16e2e72cbdfb889406754f9785d7f3c68fc7bfd7 100644
--- a/DSTAT-temp/src/config/conf_clock.h
+++ b/DSTAT-temp/src/config/conf_clock.h
@@ -44,22 +44,22 @@
 #define CONF_CLOCK_H_INCLUDED
 
 //#define CONFIG_SYSCLK_SOURCE          SYSCLK_SRC_RC2MHZ
-#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_RC32MHZ
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_RC32MHZ
 //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_RC32KHZ
 //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_XOSC
-//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL
+#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL
 
 /* Fbus = Fsys / (2 ^ BUS_div) */
 #define CONFIG_SYSCLK_PSADIV          SYSCLK_PSADIV_1
 #define CONFIG_SYSCLK_PSBCDIV         SYSCLK_PSBCDIV_1_1
 
 //#define CONFIG_PLL0_SOURCE          PLL_SRC_XOSC
-//#define CONFIG_PLL0_SOURCE          PLL_SRC_RC2MHZ
+#define CONFIG_PLL0_SOURCE          PLL_SRC_RC2MHZ
 //#define CONFIG_PLL0_SOURCE          PLL_SRC_RC32MHZ
 
 /* Fpll = (Fclk * PLL_mul) / PLL_div */
-//#define CONFIG_PLL0_MUL             (24000000UL / BOARD_XOSC_HZ)
-//#define CONFIG_PLL0_DIV             1
+#define CONFIG_PLL0_MUL             16
+#define CONFIG_PLL0_DIV             1
 
 /* External oscillator frequency range */
 /** 0.4 to 2 MHz frequency range */
@@ -72,7 +72,7 @@
 //#define CONFIG_XOSC_RANGE XOSC_RANGE_12TO16
 
 /* DFLL autocalibration */
-//#define CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC  OSC_ID_RC32KHZ
+#define CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC  OSC_ID_RC32KHZ
 //#define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC OSC_ID_XOSC
 
 /* The following example clock configuration definitions can be used in XMEGA