From f9f3e216fe23d8406d1063e67f819a98de96b956 Mon Sep 17 00:00:00 2001 From: Michael Dryden Date: Wed, 9 Jul 2014 14:48:10 -0400 Subject: [PATCH] Fixed typo. Was checking if preconditioning voltages were above zero instead of times. --- DSTAT-temp/src/experiment.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/DSTAT-temp/src/experiment.c b/DSTAT-temp/src/experiment.c index 4330646..a262d0f 100644 --- a/DSTAT-temp/src/experiment.c +++ b/DSTAT-temp/src/experiment.c @@ -248,7 +248,7 @@ void precond(int16_t v1, uint16_t t1, int16_t v2, uint16_t t2){ //assumes potent up = 1; //first potential - if (v1 > 0){ + if (t1 > 0){ max5443_set_voltage1(v1); rtc_set_alarm(t1); RTC.CNT = 0; @@ -271,7 +271,7 @@ void precond(int16_t v1, uint16_t t1, int16_t v2, uint16_t t2){ //assumes potent up = 1; time_old = 0; - if (v2 > 0){ + if (t2 > 0){ max5443_set_voltage1(v2); rtc_set_alarm(t2); RTC.CNT = 0; -- GitLab