experiment: Switch TC module to free up TCC0 for frequency generation.

src/experiment.c

@@ -603,36 +603,36 @@ uint8_t lsv_experiment(int16_t start, int16_t stop, uint16_t slope, int8_t first
 		portd_int0_callback = porte_int0_lsv; //ADC read
 
 		//set EVCH0 event
-		EVSYS.CH0MUX = EVSYS_CHMUX_TCC0_OVF_gc;
+		EVSYS.CH0MUX = EVSYS_CHMUX_TCD0_OVF_gc;
 		EVSYS.CH0CTRL = 0;
 
 		timer_period = ceil(1/((double)slope/(3000./65536))*(F_CPU));
 		temp_div = ceil(timer_period/65536.);
 		
 		if (temp_div <= 1)
-			tc_write_clock_source(&TCC0,TC_CLKSEL_DIV1_gc);
+			tc_write_clock_source(&EXP_TC0_0,TC_CLKSEL_DIV1_gc);
 		else if (temp_div == 2){
-			tc_write_clock_source(&TCC0,TC_CLKSEL_DIV2_gc);
+			tc_write_clock_source(&EXP_TC0_0,TC_CLKSEL_DIV2_gc);
 			timer_period /= 2;
 		}
 		else if (temp_div <= 4){
-			tc_write_clock_source(&TCC0,TC_CLKSEL_DIV4_gc);
+			tc_write_clock_source(&EXP_TC0_0,TC_CLKSEL_DIV4_gc);
 			timer_period /= 4;
 		}
 		else if (temp_div <= 8){
-			tc_write_clock_source(&TCC0,TC_CLKSEL_DIV8_gc);
+			tc_write_clock_source(&EXP_TC0_0,TC_CLKSEL_DIV8_gc);
 			timer_period /= 8;
 		}
 		else if (temp_div <= 64){
-			tc_write_clock_source(&TCC0,TC_CLKSEL_DIV64_gc);
+			tc_write_clock_source(&EXP_TC0_0,TC_CLKSEL_DIV64_gc);
 			timer_period /= 64;
 		}
 		else if (temp_div <= 256){
-			tc_write_clock_source(&TCC0,TC_CLKSEL_DIV256_gc);
+			tc_write_clock_source(&EXP_TC0_0,TC_CLKSEL_DIV256_gc);
 			timer_period /= 256;
 		}
 		else if (temp_div <= 1024){
-			tc_write_clock_source(&TCC0,TC_CLKSEL_DIV1024_gc);
+			tc_write_clock_source(&EXP_TC0_0,TC_CLKSEL_DIV1024_gc);
 			timer_period /= 1024;
 		}
 		else{

src/experiment.h

@@ -77,8 +77,8 @@
 
 #define RTC_COMPARE_INT_LEVEL RTC_COMPINTLVL_HI_gc
 
-#define EXP_TC0_0       TCC0
-#define EXP_TC1_0       TCC1
+#define EXP_TC0_0       TCD0
+#define EXP_TC1_0       TCD1
 #define EXP_TC0_1       TCF0
 
 extern uint16_t g_gain;